`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/11 13:30:13
// Design Name: 
// Module Name: rgb_gray
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module rgb_gray#(
PROC_METHOD="average"
)
(
input clk,
input rst_p,
input [7:0]rgb_red,
input [7:0]rgb_green,
input [7:0]rgb_blue,
input image_hs,
input image_vs,
input image_valid,

output [7:0]rgb_gray,
output reg rgb_valid,
output reg rgb_hs,
output reg rgb_vs
    );
generate     
if(PROC_METHOD=="average")begin:average
wire [9:0]sum;
reg [15:0]rgb_gray_r;
assign sum = rgb_red + rgb_green + rgb_blue;
always@(posedge clk or posedge rst_p)begin
if(rst_p)
rgb_gray_r <= 16'b0;
else if(image_valid)
rgb_gray_r <= (sum<<6) +(sum<<4) + (sum<<2) +sum;
end

assign rgb_gray = rgb_gray_r[15:8];

always@(posedge clk)begin
rgb_hs <=image_hs;
rgb_vs <= image_vs;
rgb_valid <= image_valid;
end

end
//------------------------------------------
else if(PROC_METHOD=="formula")begin:formula
reg[15:0]rgb_gray_r;
wire [15:0]rgb_red_x77;
wire [15:0]rgb_green_x150;
wire [14:0]rgb_blue_x29;
assign rgb_red_x77 = (rgb_red<<6) + (rgb_red<<3) + (rgb_red <<2) + (rgb_red);
assign rgb_green_x150 = (rgb_green <<7) + (rgb_green<<4) +(rgb_green<<2) + (rgb_green <<1);
assign rgb_blue_x29 = (rgb_blue <<4) + (rgb_blue <<3) + (rgb_blue <<2) + rgb_blue;

always@(posedge clk or posedge rst_p)begin
if(rst_p)
rgb_gray_r <= 16'b0;
else if(image_valid)
rgb_gray_r <= rgb_red_x77 +rgb_green_x150 + rgb_blue_x29;
end

assign rgb_gray = rgb_gray_r[15:8];

always@(posedge clk)begin
rgb_hs <=image_hs;
rgb_vs <= image_vs;
rgb_valid <= image_valid;
end

end
//_____________________________________________
//else if(PROC_METHOD=="LUT")begin:LUT
//wire [14:0]rgb_red_x77;
//wire [15:0]rgb_green_x150;
//wire [13:0]rgb_blue_x29;
//reg [15:0]rgb_gray_r;
//romblue_x29 romblue_x291 (
//  .clka(clk),    // input wire clka
//  .ena(image_valid),      // input wire ena
//  .addra(rgb_blue),  // input wire [7 : 0] addra
//  .douta(rgb_blue_x29)  // output wire [13 : 0] douta
//);

//romgreen_x150 romgreen_x1501 (
//  .clka(clk),    // input wire clka
//  .ena(image_valid),      // input wire ena
//  .addra(rgb_green),  // input wire [7 : 0] addra
//  .douta(rgb_green_x150)  // output wire [15 : 0] douta
//);

//romred_x77 romred_x771 (
//  .clka(clk),    // input wire clka
//  .ena(image_valid),      // input wire ena
//  .addra(rgb_red),  // input wire [7 : 0] addra
//  .douta(rgb_red_x77)  // output wire [14 : 0] douta
//);

//always@(posedge clk or posedge rst_p)begin
//if(rst_p)
//rgb_gray_r <= 16'b0;
//else if(image_valid)
//rgb_gray_r <= rgb_red_x77 +rgb_green_x150 +rgb_blue_x29;
//end

//assign rgb_gray =rgb_gray_r[15:8];

//reg rgb_hs1;
//reg rgb_vs1;
//reg rgb_valid1;
//always@(posedge clk)begin
//rgb_hs1 <=image_hs;
//rgb_vs1 <= image_vs;
//rgb_valid1 <= image_valid;
//end

//always@(posedge clk)begin
//rgb_hs <=rgb_hs1;
//rgb_vs <= rgb_vs1;
//rgb_valid <= rgb_valid1;
//end

//end

else begin:PRO_NONE
assign rgb_gray = 8'h00;

always@(posedge clk)begin
rgb_hs <=image_hs;
rgb_vs <= image_vs;
rgb_valid <= image_valid;
end

end

endgenerate

endmodule
